Synopsys announces that its silicon-proven DesignWare DDR5/4 PHY IP would be utilized by Mellanox, recently acquired by U.S. chip supplier NVIDIA Corp for $6.9 billion. To determine memory prerequisite issues in the InfiniBand organizing chips for superior processing and artificial intelligence applications, the NVIDIA’s networking business unit settled the use of DesignWare.
DesignWare DDR5/4 IP supporting multiple DIMMs per channel with an 80-bit data path is designed to fix the issues pertaining to data rate and memory capacity requirements as NVIDIA magnifies its efforts in cloud computing and high performance. As a piece of Synopsys’ wide memory interfaces IP portfolio with controllers, verification IP and PHYs for a wide scope of procedures help the fundamental features to assist Mellanox to acclimatize the IP into ASICs and SoCs with a diminished measure of hazard.
Improved for low force, high data transfer limit, and augmented flagging highlights, the DesignWare DDR Memory Interface IP arrangement comprises of a choice of flexible propelled controllers and verification IP. It additionally conveys firmware-based preparation, which is field upgradeable without expecting changes to the hardware of helping clients lessen the danger of embracing the most recent protocols.
Firmware-based training allows for the usage of intricate training patterns, allowing channel reliability and a higher margin at the system level. Synopsys’ DDR5/4 PHY IP offers different low-power states with smaller exit latencies for power- profitability and various pre-arranged statuses for dynamic recurrence conversion competence.
John Koeter, senior VP of marketing and strategy for IP at Synopsys, states, “High-performance ASICs and SoCs for data-intensive networking and artificial intelligence applications require high-bandwidth off-chip memory technologies that efficiently minimize performance bottlenecks. The DesignWare DDR5/4 PHY IP, operating at maximum data rates with differentiated features like firmware-based training, allows companies like NVIDIA to implement the latest functionality in their designs with less risk.”
Shlomit Weiss, senior VP of engineering at Mellanox business, adds, “Our choice of Synopsys’ DesignWare IP for our latest InfiniBand solutions with in-network computing capabilities builds on our long history of integrating their high-quality IP into our silicon. Synopsys’ DDR PHY IP is the best available solution to help us overcome stringent memory requirements while giving us the quality, capacity, and performance we need to deliver differentiated products.”
As of late, the organization likewise uncovered the business’ broad arrangement of top-notch IP on TSMC’s 5nm procedure innovation for top-execution figuring SoCs. DesignWare IP portfolio on the TSMC, with interface IP for high-speed protocols and foundation IP, quickens the development of SoCs for AI accelerators, high-end cloud computing, storage, and networking applications.
Suk Lee, senior director of the Design Infrastructure Management Division at TSMC, says. “Our long-term collaboration with Synopsys has resulted in delivering DesignWare IP on the most advanced TSMC processes, enabling our mutual customers to achieve many first-pass silicon successes in a wide range of markets, including high-performance computing.”
To speak of the originator, Synopsys is one of the main suppliers of top-quality, silicon-proven IP solutions for the overall SoC designs. Their far-reaching DesignWare IP portfolio comprises embedded memories, implanted test, installed processors, logic libraries, wired and remote interface IP, analog IP, security IP, and subsystems. Its widespread investment in all-inclusive technical support, superior IP quality, and secure IP development procedure let designers lessen integration risk and hasten time-to-market.
